Abstract – Hardware acceleration on Artificial Intelligence (AI) has become an indispensable technique for a wide range of real-time applications such as video classification, speech recognition, and autonomous robot. Specifically in the era of edge computing, to limit the complexity of AI algorithms in the power-constrained and latency-critical scenarios is a big challenge. Therefore, this presentation focuses on mapping neural networks onto field-programmable gate array (FPGA) with the benefits of high parallelism and programmability. Generally, two research subjects are discussed: the design and evaluation to FPGA acceleration and system-on-chip (SoC) architecture to FPGA. First, case studies to the design on FPGA accelerator are presented, including handwritten digit recognition and real-time music transcription. Second, a low-cost and energy-efficient SoC architecture is discussed to the applications of edge devices. By integrating DMA, AES core, bus wrappers, and open verification components (OVCs), a UVM-based environment is finally established to verify the functionality of the SoC.

Dr. Xiaokun Yang received his Ph.D. from the Department of Electrical and Computer Engineering (ECE), Florida International University (FIU), USA in Spring 2016. He is currently an Assistant Professor at the College of Science and Engineering, University of Houston-Clear Lake. From 2007 to 2012, he has also worked as a Senior ASIC Design and Verification Engineer at Advanced Micro Devices (AMD) and China Electronic Corporation (CEC). His research interests include Hardware Acceleration on AI/ML, ASIC/FPGA Design and Verification on Neural Networks, and Energy-Efficiency System-on-Chip (SoC) Architecture. As the first author or corresponding author, Dr. Yang has published more than 50 papers including 3 patents, more than 15 peer-review journals, and more than 30 prestigious international conferences. He has served on several editorial boards and journal reviewers including IEEE Trans. on Computer, IEEE Trans. on VLSI, and IEEE Trans. on Education, and numerous conference committees including ISVLSI and ISQED.

Abstract - Everyone knows that modern digital computers are based on deterministic Boolean logic gates that are assumed to perform exact computation of logical operations such as AND, NOT etc. In this talk, we will explore two alternatives to this framework in which the demand on the output being correct on all inputs is relaxed. First, we will consider a state machine model as a way to approximate the solutions of some computational problems. The second one is a stochastic model of logic gates that provides an alternative hardware basis for building digital computers. Some applications of these models will also be presented.

Dr. Ravikumar received his Ph.D. in Computer Science from the University of Minnesota and has taught at many universities including University of Minnesota, University of Rhode Island, San Francisco State University and Sonoma State University. He has supervised many graduate and undergraduate projects. He is an editor of the International Journal of the Foundations of Computer Science and has served on the program committees of many international conferences. He has presented invited and contributed talks in more than fifty international conferences.